Heretofore, higher integration of a logic LSI and a nonvolatile memory LSI has been realized by reducing sizes of devices constituting them. In recent years, however, difficulty of fine pattern processing has increased, and device stacking (LSI three-dimensional stacking) has extensively been investigated as a technique of enhancing the integration without relying on fineness.
In general, an active layer of a transistor or a diode constituting the three-dimensional structure LSI is a semiconductor surrounded with an insulator, but to realize the higher integration, it is necessary to reduce the size of the semiconductor. In consequence, the semiconductor as the active layer often becomes a fine wire (nanowire) shape having a size of several tens of nanometers or less. When the active layer has the nanowire shape, a wiring section for accessing the individual devices also has the nanowire shape, but it is known that it is difficult to implant a highly concentrated impurity in the semiconductor having the nanowire shape, and the resistance of the semiconductor becomes high. When the resistance of the wiring section becomes high, the deterioration of an operation speed of the LSI becomes a problem.
To lower the resistance of the wiring section, it can be contrived that the wiring section is made of a metal, but the fine pattern processing of the metal is very difficult. Accordingly, a technology of forming a fine wiring line of a low resistance by a simple process is required.